Is the Complicated ECC Array Necessary for Data Caches?

Abstract We propose a power-aware ECC (Error Correction Code) register without hurting the reliability of data caches. The ECC register replaces the complicated ECC array used in traditional data caches. While the traditional ECC in the ECC array is dedicated to one cache line, the proposed ECC register is shared by all the cache lines, which significantly reduces leakage power consumed in the ECC array. The simulation results show that the proposed ECC register consistently saves 8.5% of total power consumption in the 32KB data cache. On occurrence of a soft error, all the cache lines and the ECC register should be read to correct the soft error. However, the performance overhead from reading all the cache lines is negligible, since the Soft Error Rate (SER) is 1.00E-10 in the 70nm technology.